This invention relates to a vector processing system and, more particularly, to a vector processing system capable of setting the number of storage locations to be used in vector registers.
An example of a prior art vector processing system is proposed in U.S. Pat. No. 4,128,880. The proposed system is equipped with eight vector registers each having 64 storage locations to execute vector processing for vector data within each storage location of the respective vector registers. The length of one vector register, that is, the number of storage locations in one vector register, will be referred herein to as a maximum vector length (MVL). In vector processing, in response to an instruction, the number of vector elements to be executed is first stored in storage means called a vector length register used to hold the number of vector operations to be executed. Next, the vector elements are sequentially read out of the vector registers to a vector functional unit by the number corresponding to the value stored in the vector length register, the operation (for example, an add operation, a multiplication operation and so on) specified with the instruction is executed in respect of the vector elements read out, and the results of the operation are sequentially stored in other vector register or in a main memory. Now, if the number N of repetitions of a loop part of a program written in the FORTRAN language or other programming languages is equal to or less than the MVL, the number N is stored in the vector length register, several sets of the N vector elements are stored in the vector registers specified by the instruction, respectively, and the specified operation in the program loop is executed for the N vector elements sequentially read out of the vector registers. On the other hand, if N is larger than the MVL, the value M obtained by adding "1" to the remainder of (N-1)/MVL is first stored in the vector length register to execute the first processing. In the first processing, several sets of the M vector elements are stored in the specified vector registers, respectively, and the specified operation is executed for the sets of the M vector elements. In the second processing, the MVL is then loaded by the program into the vector length register, several sets of the MVL number vector elements are stored in the specified vector registers, respectively, and the specified operation is carried out for the sets of the MVL vector elements. Such second processing is repeated [(N-1)/MVL] times with the remaining sets of the vector elements where [(N-1)/MVL] means the largest integer which does not exceed (N-1)/MVL. In this manner, although the program loop having the relation of N&gt;MVL can be processed in the prior art system, an object program must have the MVL as a constant. As a result, in order to execute the object program with some vector processing system provided with vector registers, each of which has a smaller number of storage locations than the corresponding one used in the above-mentioned prior art system, some re-compiling step of the program is indispensable to changing the MVL to be adaptable to those vector registers having such fewer number of storage locations. Generally, when vector processing systems are manufactured for commercial purposes, a plurality of design models, which are provided with vector registers having different MVLs are sometimes prepared so as to meet various demands of users at an optimal cost-performance rate. As a result, object programs corresponding to such models must be prepared, because they are not interchangeable between those models.
One object of this invention is, therefore, to provide a vector processing system free from the above-mentioned disadvantages in the prior art system.